1. Field of the Invention
The invention generally relates to methods and apparatus for interconnecting a computer system's processor and a set of devices, including memory means. The invention particularly relates to a novel bus architecture and associated control techniques that may be used to achieve a low cost, high performance interface when used in a reduced instruction set computer (RISC) system to interconnect the RISC processor and the aforesaid devices.
2. Description of the Related Art
The bus architecture of a computer system is used for interfacing the system's processor(s) with a multiplicity of devices such as memory units, coprocessors, external devices, etc. The interface typically carries address, data and instruction signals, as well as various control and status signals.
In order to support the high data and instruction processing rates on modern computer systems, in particular RISC systems, it is essential that the interface design be uncomplicated, and be capable of moving information swiftly and without delay between the computer system's components. In other words, the interface must be capable of operating with a minimum of contention, timing constraints, buffering requirements, etc. In addition, it is important that the interface be cost effective, from an implementation point of view, to complement the overall lower cost of modern day computing systems.
In known systems, where processors are fabricated as integrated circuit packages, the interfaces use a variety of multiplexed and demultiplexed busing techniques in order to minimize the number of buses required to make up the interface and maximize the performance. This in turn has the effect of minimizing the number of processor interface interconnect pins which helps keep both processor chip and system design costs down.
In the known multiplexed bus schemes, the interface typically is comprised of separate instruction and data buses. For example, for 32 bit wide instructions and data, two buses, requiring a 64 pin processor interconnect, are typically used. One of the buses carries multiplexed signals representing data addresses and data. The other bus carries multiplexed signals representing instruction addresses and instructions. The disadvantages of the multiplexed bus schemes are difficulties in clocking the information, which affects performance; the need for multiplexing hardware, which affects cost and performance; and the potential for mismatches between the timing constraints associated with multiplexing the information, and the timing constraints of the memory and other subsystems of the computer.
Systems using pairs of demultiplexed buses (again for a 64 pin example), are prone to experience instruction and data contention problems. These systems normally have instruction and data address signals carried on one shared bus, and share an instruction/data bus for the instruction and data signals themselves.
The aforesaid data contention problems are particularly serious in RISC computer environments where the processor is capable of executing pipelined and burst mode protocols. As will be explained in detail hereinafter, execution of these protocols requires two or more processing cycles, with the potential for sequential data and/or instruction transfers spanning many cycles. Using a shared instruction/data bus in these cases would dramatically slow processing time exacerbating the aforesaid contention problem.
An apparent, but expensive, solution to the aforesaid problems would be to have four buses, one each for data, instruction, data address and instruction address signals. Totally separate and independent buses eliminate the multiplexing and contention problems. However, the system's design cost would go up and, for the 32 bit word example, the processor interface would require 128 bus pins.
It would be desirable to be able to take advantage of, and support the high data and instruction processing rates characteristic of, RISC processors, by providing a high performance system interface that is low cost, minimizes contention problems, timing constraints, etc. In particular, it would be desirable to utilize an interface that takes advantage of normal RISC processor characteristics, such as a single cycle execution time, explicit memory references for load, store and branch instructions, pipelined and burst mode operation capabilities, etc., to realize the desired high performance objective.
Additionally, it would be desirable to be able to achieve, at the nominal expense of increasing bus pin count from 64 pins to 96 pins (for systems having 32 bit wide instructions and data), an interface capability approximating the capability heretofore thought possible only by using a 4 bus, 128 pin interface; while avoiding the problems of the 2 bus, 64 pin interfaces discussed hereinbefore.